20nm

April 15, 2014

Common Platform foundry alliance to be wound down

But some research and process collaboration is set to continue in the background as Samsung, GlobalFoundries and IBM chart their own priorities.
Article  |  Topics: Blog - EDA  |  Tags: , , , ,   |  Organizations: , , ,
December 16, 2013

Qualcomm’s take on preserving Moore’s Law economics

Industry-wide innovation is required to make scaling cost-effective at 7nm, says Qualcomm's VP of Technology. Time for a fat, cholesterol and MSG-free diet.
November 13, 2013

TSMC succession plan emphasizes stability

TSMC stays the course with new co-CEOs as Morris Chang retains executive leadership for now while finFET, 3D and other new technologies settle in.
Article  |  Topics: Commentary, Design to Silicon  |  Tags: , , , , , , , ,   |  Organizations: , , ,
October 4, 2013

Design kit for 10nm FD-SOI due out next year

Research group CEA-Leti expects to have design kits ready for a 10nm FD-SOI process in June 2014
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July 15, 2013

Electrically aware Virtuoso aims to head off physical issues

Cadence Design Systems has rolled out a new version of Virtuoso that deals with the physical-implementation issues that arise in the sub-28nm nodes.
June 10, 2013

Altera outlines process roadmap for ‘Gen 10′ FPGAs

Altera has disclosed a number of the features that will make it into the top end of its upcoming 'Generation 10' family of FPGAs.
Article  |  Topics: Blog - EDA, PCB  |  Tags: , , , , ,   |  Organizations: , ,
June 5, 2013

FinFET processes demand delicate tradeoffs for mobile SoCs – GlobalFoundries process architect

The increasing use of graphics in mobile SoCs means that finFET processes need to be optimised for density and power - as well as early availability at low risk.
Article  |  Topics: Blog - EDA, IP  |  Tags: , , ,   |  Organizations:
March 20, 2013

DATE: Double patterning and finFETs force flexibility on tools

EDA companies are having to plan for the different ways in which double patterning and finFETs could move into fabs, Antun Domic of Synopsys explains.
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March 20, 2013

DATE: Early shift to finFET processes challenges IP development strategies

An early shift to finFET processes is making developing IP libraries more challenging.
Article  |  Topics: Conferences, Blog - EDA  |  Tags: , , , , , , , ,   |  Organizations:
January 28, 2013

Cadence updates Virtuoso for the 20nm generation

Cadence Design Systems has built into its latest Virtuoso update features designed to tackle the problems of working with the 20nm generation of processes with finer control over layout-dependent effects, double patterning and new types of local interconnect.

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