EDA companies are having to plan for the different ways in which double patterning and finFETs could move into fabs, Antun Domic of Synopsys explains.
An early shift to finFET processes is making developing IP libraries more challenging.
Cadence Design Systems has built into its latest Virtuoso update features designed to tackle the problems of working with the 20nm generation of processes with finer control over layout-dependent effects, double patterning and new types of local interconnect.
20nm design is fraught with problems for analog design but one that causes the biggest headaches is density variation, says Synopsys' Joachim Kunkel.
finFETs are vital to the next generation of CMOS processes from Intel, TSMC and others. How will process issues including bulk vs SOI substrates, density limitations, thickness control, and planar device integration affect their practical implementation?
The Mentor chief discusses ESL-based low power, emulation, 32nm to 20nm and using tools in the cloud.
IP and EDA vendors line up to support TSMC 20nm process, CoWoS 3DIC technology
Intel finFET family grows to support SoC use, as TSMC boosts p-channel performance with germanium
Manufacturability, routing, library design and more - it all needs rethinking at 20nm
TSMC has released two reference flows – one for its 20nm and the other for the form of 3D integration favored by the Taiwanese foundry, chip on wafer on substrate (CoWoS).
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