TSMC stays the course with new co-CEOs as Morris Chang retains executive leadership for now while finFET, 3D and other new technologies settle in.
Research group CEA-Leti expects to have design kits ready for a 10nm FD-SOI process in June 2014
Cadence Design Systems has rolled out a new version of Virtuoso that deals with the physical-implementation issues that arise in the sub-28nm nodes.
Altera has disclosed a number of the features that will make it into the top end of its upcoming 'Generation 10' family of FPGAs.
The increasing use of graphics in mobile SoCs means that finFET processes need to be optimised for density and power - as well as early availability at low risk.
EDA companies are having to plan for the different ways in which double patterning and finFETs could move into fabs, Antun Domic of Synopsys explains.
An early shift to finFET processes is making developing IP libraries more challenging.
Cadence Design Systems has built into its latest Virtuoso update features designed to tackle the problems of working with the 20nm generation of processes with finer control over layout-dependent effects, double patterning and new types of local interconnect.
20nm design is fraught with problems for analog design but one that causes the biggest headaches is density variation, says Synopsys' Joachim Kunkel.
finFETs are vital to the next generation of CMOS processes from Intel, TSMC and others. How will process issues including bulk vs SOI substrates, density limitations, thickness control, and planar device integration affect their practical implementation?
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