20nm

August 18, 2014

Power and clocking at 20nm force changes in FPGAs

Design for the 20nm generation of processes has revealed power and clocking issues for the two major FPGA manufacturers presentations at Hot Chips revealed.
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June 20, 2014

14nm FD-SOI pushes strain and body bias for power savings

At the VLSI Technology Symposium a team led by STMicroelectronics described the techniques used for the upcoming 14nm FD-SOI to boost speed and density over the 28nm version.
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June 3, 2014

Remember 20nm? Qualcomm does

Qualcomm will present at VLSI Technology Symposium 2014 a version of TSMC's 20nm technology that uses design and process tweaks to reduce the number of double-patterned layers.
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April 15, 2014

Common Platform foundry alliance to be wound down

But some research and process collaboration is set to continue in the background as Samsung, GlobalFoundries and IBM chart their own priorities.
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December 16, 2013

Qualcomm’s take on preserving Moore’s Law economics

Industry-wide innovation is required to make scaling cost-effective at 7nm, says Qualcomm's VP of Technology. Time for a fat, cholesterol and MSG-free diet.
November 13, 2013

TSMC succession plan emphasizes stability

TSMC stays the course with new co-CEOs as Morris Chang retains executive leadership for now while finFET, 3D and other new technologies settle in.
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October 4, 2013

Design kit for 10nm FD-SOI due out next year

Research group CEA-Leti expects to have design kits ready for a 10nm FD-SOI process in June 2014
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July 15, 2013

Electrically aware Virtuoso aims to head off physical issues

Cadence Design Systems has rolled out a new version of Virtuoso that deals with the physical-implementation issues that arise in the sub-28nm nodes.
June 10, 2013

Altera outlines process roadmap for ‘Gen 10′ FPGAs

Altera has disclosed a number of the features that will make it into the top end of its upcoming 'Generation 10' family of FPGAs.
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June 5, 2013

FinFET processes demand delicate tradeoffs for mobile SoCs – GlobalFoundries process architect

The increasing use of graphics in mobile SoCs means that finFET processes need to be optimised for density and power - as well as early availability at low risk.
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