A year on from the last Computex and the launch of the Cortex-A73 and Mali-G71, ARM has launched a new trio of processors aimed not just at smartphones this time but servers and driver-assistance systems.
Machine learning, smarter cars, and the infrastructure to support a sixfold increase in IoT and edge devices have helped push up the number of teams doing finFET designs to more than 100, according to Tom Beckley of Cadence.
Menta SAS has launched an embedded FPGA core family that improves density over previous versions.
Cadence has use physically aware placement in a test tool that promises less routing congestion for scan test and which increases the potential for stimulus compression.
Rapid virtual prototyping and a metal stack that's more designer friendly are two of the ways in which Samsung aims to build up foundry market share for its 14nm and 10nm finFET processes.
HiSilicon claims close collaboration with foundry and EDA tools partners helped speed up plans to tape out the first 16nm finFET-based design through TSMC.
RTL synthesis has joined the array of tools developed by Cadence Design Systems that employ distributed processing, with the aim of exploring more ways of creating area- and power-efficient logic blocks.
The FD-SOI technology developed by CEA-Leti and STMicroelectronics is beginning to gain ground as chipmakers investigate the process as a way to deliver low-energy, wireless-capable SoCs.
As plans crystallize to take FD-SOI down to 10nm, CEA-Leti argues that the technology can provide an alternative path to that of finFETs to get to 7nm processes and beyond.
Cadence Design Systems has coupled the parallel-processing techniques behind its recently launched sign-off tools to engines intended to deal with sub-28nm process issues in a suite that reworks the company’s key implementation tools.
View All Sponsors