14nm finFET test-chip designs are moving through Samsung's fab as ARM, Cadence Design Systems and Synopsys continue to check their flows on the new process.
Can planar devices on fully depleted SOI resist the relentless rise of finFETs as the next device architecture of choice for the semiconductor industry? An evening panel at IEDM explored the trade-offs
Semiconductor process options outlined at IEDM by Luc van den Hove of imec as industry faces hard choices and rising costs
finFETs are vital to the next generation of CMOS processes from Intel, TSMC and others. How will process issues including bulk vs SOI substrates, density limitations, thickness control, and planar device integration affect their practical implementation?
Ever increasing lithography challenges mean the next generation of design rules may concentrate on telling you just what you can rather than what you cannot do.
Our first email newsletter previews next month's Common Platform Technology Forum 2012 and features exclusive interviews with senior staff at Samsung, ARM and Cadence Design Systems.
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