Simulation suite automates the largely manual process of validating more than 25 SerDes protocols.
The Siemens subsidiary is involved with a wide range of tutorials, technical papers and more at this month’s San Jose conference.
Traditional functional coverage has run out of steam and novel methods to improve the understanding of what tests are doing are needed to make progress. That is the view of Greg Smith, director of verification innovation and methodology improvement at Oracle.
Metrics Technologies has launched as a supplier of cloud-based verification tools offering per-minute pricing.
Movellus has launched the first of a series of IP-creation tools with one that will build all-digital PLLs and integrate them into a design.
UltraSoC has released its first implementation of processor trace for cores based on the RISC-V instruction set.
ARM and Mentor describe a proof-of-concept project using free tools and IP to combine AMS and digital.
Struggling with how to make your debug triage process more efficient? A new checklist could help focus your efforts.
If current market trends persist, shortages in wafers are likely to follow, hurting the ability of some companies to ship silicon and boost the prices for those who can.
Codasip has launched the seventh generation of its Studio software for processor design and tuning, aiming to take advantage of the interest in RISC-V as a core instruction set for customized processors.
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