Three Mentor divisions – Embedded, PADS and Tanner EDA – will present their latest innovations during the conference and exhibition in Nuremberg next week.
Formal enables substantial fault pruning and more definitive fault injection for ISO 26262 using techniques such as sequential logic equivalence checking.
Cadence has reworked two parts of its verification suite to streamline the use of multicore computers for simulation and FPGA-based prototyping systems.
Ceva’s latest iteration of its XC architecture aims at the intensive DSP required for 5G basestations.
Analog fault simulation times have barely fallen for two decades but that is beginning to change.
Xilinx plans to add high-speed analog interfaces to its upcoming FPGAs to better support high-density 5G basestation designs.
StratoM hardware has 2.5B-gate capacity and can scale to 15B gates. Throughput claimed at 5X faster than earlier Veloce generation.
The major verification conference is looming and Mentor’s participation will include tutorials that explore the latest in portable stimulus, SystemC, VIP and more.
Intrinsic-ID has developed software that allows its PUF technology to be used in most systems that contain static memory together with a framework for managing secure keys in the supply chain.
Microsemi has launched a family of non-volatile FPGAs that use a 28nm process to increase density over the previous SmartFusion devices.
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