Early access to tools for new processes is helping Moortec deliver IP to determine the real-time health of on-chip circuits.
It’s been a long time coming, but silicon photonics is now entering commercial design for networking and grabbing attention in autonomous driving and sensors.
A report put together by Europe’s HiPEAC high-performance computing research network argues computing is at an architectural turning point
Data-centre networking chip goes through full-chip design rule checking and layout-versus-schematic signoff on TSMC’s 16nm finFET process in a day.
Physical verification challenge of large SoCs on leading-edge processes detailed in video series
Ceva has followed its IoT-oriented Ceva-X series of processor cores with a more powerful family that is designed to handle control and signal-processing algorithms using the same pipeline.
Closing code coverage from HLS has been tricky because the C++ tools were built for software not hardware. But that is changing.
With PSS moving toward greater adoption, the Siemens vendor seems PSS-DSL as a winner in terms of conciseness and ease-of-adoption.
Synopsys is targeting artificial intelligence (AI) and data centre SoCs as key application areas for the interface IP.
Embedded magnetic RAM is emerging as a contender for on-chip memory not just from a density standpoint but from that of power.
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