Video series details the physical verification process

By TDF Editor |  No Comments  |  Posted: January 21, 2019
Topics/Categories: Blog - EDA, - Verification  |  Tags: , , ,  | Organizations:

Synopsys has released a set of short videos that outlines some of the challenges of validating the largest and most complex chips implemented on the latest processes – and some of the potential solutions.

Representatives from IBM, Juniper, NVIDIA, and Socionext discuss how tools such as Synopsys’ IC Validator have enabled them to complete the physical verification process on very large chips –­ including NVIDIA’s reticle-limited G100 GPU.

There are also a couple of videos discussing issues such as managing the trade-off between adding metal fill to improve SoC manufacturability and the impact of doing so on the timing of critical nets and on how to reduce the time it takes to fix issues thrown up DRC.

Synopsys has also created a set of short videos on detailed issues to do with using its physical verification tools, focusing on topics such as DRC,  LVS, fill, the VUE user interface, applying veracious verification features in design, how to use pattern-matching strategies, the advantages of distributed processing, applying waivers, and using the PYDB physical database.

The video series also includes an overview of some its tools’ functions, and an outline of where to find various forms of documentation.

 

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