At the International Electron Device Meeting (IEDM) this week CEA-Leti claimed to have achieved major steps in bringing monolithic 3D integration closer to production readiness.
For a number of years, Leti has been working on the technology through the CoolCube program. The aim is to double chip density at a given process node by stacking two CMOS layers on top of each other. Knock-on reductions in wire length are expected to help save 26 per cent in power and improve yield. The main challenge is finding a way to fabricate a second layer without damaging the first when it goes through high-temperature annealing steps. The latest work uses layer transfer to introduce the second layer of transistors, which reduces the high-temperature steps mainly to gate formation and connection.
Image Leti's CoolCube integration flow
The team also worked on an intermediate routing based on existing copper-interconnect materials to connect the two layers, with the aim of improving flexibility. The problem with introducing local routing below a second CMOS layer is that the copper and ultralow-k dielectrics can contaminate the surfaces. They also cannot survive conventional high-temperature processing.
The changes Leti has made recently include the use of a low-resistance polysilicon gate for the top transistors together with lower-temperature processes for creating raised source and drain areas. Annealing steps were performed using a UV nanosecond laser. Epitaxy was changed so that it can happen efficiently at lower temperatures. The team demonstrated this using new silicon precursor and dichlorine etching.
To deal with the contamination problem after depositing local routing, the team encapsulated the top surface of the wafer and took steps to avoid damage to the bevel on the wafer's edge from releasing the contaminants into the FEOL process equipment.