White paper outlines challenges of developing machine-learning hardware

By TDF Editor |  No Comments  |  Posted: October 2, 2018
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A recent white paper from Synopsys outlines the complexities of developing hardware for use in machine-learning and artificial-intelligence (AI) systems.

The article looks at the very different requirements for AI acceleration in neural networking training, often carried out in large data centres, and inferencing using trained networks, often carried out in devices at the age of the network. The design constraints in this two cases are very different, with latency and power consumption being much more important in edge devices than in data centre accelerators.

The white paper goes on to explore the challenge of developing custom hardware in an environment in which the key deep-learning algorithms are changing very rapidly. The trick, the paper's authors argue, is to design an accelerator architecture that makes the right tradeoff between computational power, energy consumption, memory bandwidth, and external interconnect, Again, the right balance will be different for data centre devices and edge devices.

The authors then move on to discuss the physical design challenges of implementing the chosen architectures. In data centre AI accelerators, designers may be working with tens of billions transistors and very high clock rates, leading to power dissipation issues. For inferencing engines in edge devices, the challenge may be ensuring the device is effective at externe temperature and voltage corners.

The paper is rounded out with a discussion of various tools that Synopsys offers to help designers implement their chosen architectures. These include ASIP Designer, which can be used to explore the efficacy of different architectures, the ZeBu emulation system, and the Synopsys Design Platform for physical implementation.

Read the white paper  here.

 

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