IBM and Synopsys to apply DTCO to post-finFET process development

By TDF Editor |  No Comments  |  Posted: August 16, 2018
Topics/Categories: Design to Silicon  |  Tags: , , , ,  | Organizations: ,

IBM and Synopsys have signed a deal to apply design technology co-optimization (DTCO) strategies to the development of post-finFET processes, in response to the increasing challenge of making good tradeoffs between the needs of IC designers and process developers at advanced nodes. DTCO provides a way to evaluate combinations of transistor architectures, materials and other process technology innovations using design metrics, before real wafers become available for physical experimentation.

The IBM/Synopsys collaboration will extend the current Synopsys DTCO tool flow to new transistor architectures and other technology options, and enable IBM to develop early process design kits with which partners will be able to assess the power, performance, area, and cost (PPAC) benefits of proposed nodes.

"Process technology development beyond 7nm requires the exploration of new materials and transistor architectures to achieve optimum manufacturability, power, performance, area, and cost. A major challenge for foundries is to converge on the best architecture in a timely manner while vetting all the possible options," said Dr Mukesh Khare, vice president of Semiconductor Research, IBM Research Lab. "Our DTCO collaboration with Synopsys allows us to efficiently select the best transistor architecture and process options based on metrics derived from typical building blocks, such as CPU cores, thus contributing to faster process development at reduced cost."

As part of this collaboration, IBM and Synopsys will jointly develop and validate new patterning techniques with Proteus mask synthesis, model alternative materials with QuantumATK, optimize transistor architectures with Sentaurus TCAD and Process Explorer, and extract compact models with Mystic. Design rules and process assumptions derived from these innovations will then be used to design and characterize a standard-cell library. The evaluation of the impact of PPAC at the block level will then be assessed using Fusion Technology, a physical implementation flow based on IC Compiler II place-and-route, StarRC extraction, SiliconSmart characterization, PrimeTime signoff, and IC Validator physical verification.

The agreement covers many other types of  design/process trade-off. These include using DTCO to optimize transistor- and cell-level design against routability, power, timing, and area, and the evaluation and optimization of  transistor architectures, including gate-all-around nanowires and nanoslab devices, with process and device simulation.

The agreement will also look at ways to optimize variation-aware models for SPICE simulation, parasitic extraction, library characterization, and static timing analysis to accurately encapsulate the effects of variation on timing and power for highest-reliability design with least over-design and design flow runtime overhead. Another aspect of the partnership will gather gate-level design metrics to refine the models, library architecture, and design flows to maximize PPAC benefits.

Dr Antun Domic, chief technology officer at Synopsys, said: "IBM's extensive process development and design know-how makes them an ideal partner for extending our DTCO solution to post-finFET technologies."

For more information on DTCO, visit www.synopsys.com/DTCO.

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