Synopsys has launched a 56G Ethernet PHY IP for use in 400Gbit/s hyperscale data centre SoCs.
The PHY uses Synopsys' silicon-proven analog-to-digital converters, with a configurable transmitter and DSP-based receiver. It supports PAM-4 and NRZ signaling, and can be used with optical and copper cable, as well as backplane interfaces for top-of-rack switches.
To meet the bandwidth needs of hyperscale data centres built with a leaf-spine architecture, the PHY supports single and aggregated link rates for 10Gbit/s to 400Gbit/s Ethernet. Synopsys says the PHY exceeds the performance requirements of the OIF and IEEE standards for chip-to-chip, backplane, and copper/optical cable interfaces.
The 56G Ethernet PHY receiver has a multi-loop clock and data recovery circuit, and DSP, to enable more robust timing recovery and better jitter performance. The architecture of the PAM-4 transmitter enables precise feed-forward equalization to meet channel performance requirements. Synopsys says the PHY's scalable architecture will also provide a foundation for next-generation 800Gbit/s Ethernet applications requiring 112G connectivity.
"The growing amount of bandwidth required in the data center is increasing the workload demand on the network infrastructure," said John Koeter, vice president of marketing for IP at Synopsys. "Synopsys' DesignWare 56G Ethernet IP allows designers to meet the high-performance Ethernet connectivity requirements of 400G hyperscale data center SoCs with less risk."
The silicon design kit for the DesignWare 56G Ethernet PHY in 16nm and 7nm finFET processes are due to be available in Q3 of 2018 and Q4 of 2018, respectively.