EDA needs to work on the back end, says Qualcomm

By Chris Edwards |  No Comments  |  Posted: June 27, 2018
Topics/Categories: Blog - EDA, PCB  |  Tags: , , , , ,  | Organizations:

It’s the back end that needs work as system-level considerations begin to dominate design, argued Qualcomm’s vice president of engineering in a short Visionary Talk on Wednesday at the Design Automation Conference (DAC).

PR ‘Chidi’ Chidambaram said the trend was being driven by a  combination of a slowdown in Moore’s Law and a focus on markets that need greater durability. “The upcoming markets are in automobiles and IoT, where products will be with people for ten years or more. We have to start thinking about designing for durability. The DPPM failure rate has to drop below 1ppm. We have DTCO [design-technology co-optimization] but more is needed.”

Communications will remain a huge market for semiconductors, Chidambaram said, but the focus is now moving away from the core SoC to the numerous interface ICs now needed to deal with multiple bands and antennas in 5G handsets. That, in turn, leads to a growing need for systems-in-package technologies that are cheaper and more reliable.

“Chip and substrate interactions cause a lot of stress. The modeling of this is not as mature as the modeling in other parts [of EDA],” Chidambaram noted, adding that the metal stack inside individual ICs also needs attention. “Modeling of the behavior of the back-end of line is not as mature as that for the front-end.”

Better metal models

He said modeling of effects such as quantum confinment in nanometer-scale fins now achieves high accuracy. “I can predict behavior to within 2 or 3 percent accuracy. But as I get into the metal the error increases a lot. The juice generated by the fin[FET] doesn’t get to the user. It’s all sucked up by the back end.”

Designers need to add significant margins to account for via parasitics, he said. “The error you get is 5 to 10 per cent on the worst-case paths. And these are the paths that matter. All this manifests in an unpredictability that we have to design for. You always end up with a wide tail that you can’t predict. So we end up over-margining the part. Getting better predictability will help us scale.”

Although novel devices such as gate-all-around and negative-capacitance transistors are likely to help bring down power, Chidambaram said, “they are not killer solutions”.

“The opportunity is for system-level innovation to drive the scaling forward. A lot of the key technologies exist today. We have packaging technologies that can integrate these different chips together. But just putting them together I don’t see a lot of benefit. Can I split the functions up differently? Maybe we can use innovation in packaging to fit all these things together.”

Leave a Comment

PLATINUM SPONSORS

Synopsys Cadence Design Systems Mentor - A Siemens Business
View All Sponsors