After initial work with Infineon Technologies, Cadence Design Systems has launched the first phase of a rollout of a suite of design tools for mixed-signal reliability analysis.
The Legato suite has three focus areas: device test; thermal simulation; and aging analysis. Work is proceeding alongside standards groups to identify methods for building fault models for efficient simulation and for assessing the risk of aging based on long-term usage.
Art Schaldenbrand, senior product manager for circuit simulation at Cadence, said the company has had analog fault simulation for some time “but customers haven’t been able to adopt it. We went to our customers and asked why isn’t fault simulation enough?”
Ongoing work is attempting to build fault models suitable for applications such as automotive. “We are coming up with ways to identify where defects can exist in a circuit. We developed technology to look at the structure of the chip to identify where the defects can appear, pass them to the simulator and then analyze the coverage.”
The work is being informed by work on the IEEE 2427 committee. “They are defining standard models for manufacturing defects,” Schaldenbrand said. “Customers will tune them for specific processes.”
Hany Elhak, product management director for Virtuoso front-end and Spectra, said the company’s approach to aging analysis looks at the combination of different reliability effects in concert with process variation.
Vinod Kariat, corporate vice president of R&D at Cadence, said: “You can see the distribution of parts to give a better idea of what happens as the product ages in the field.”
In the first iteration of Legato, aging analysis is based on transient simulation. Schaldenbrand noted that the work on mission profiles being undertaken by automotive companies will tune the analysis by taking into account the duty cycles of different cycles. “That will take a while to standardize,” he added.
As the aging behavior of finFETs is different to that of planar technologies, Cadence is working on a new set of aging models for those devices, Schaldenbrand said.
Schaldenbrand said the company has built its own thermal modeler that takes in layout and activity information to calculate the risk of heat stress to individual circuits.