DVCon US 2018 preview: Oski Technology

By TDF Editor |  No Comments  |  Posted: February 15, 2018
Topics/Categories: Conferences, Blog - EDA, - Verification  |  Tags: ,  | Organizations: ,

Oski Technology will demonstrate its Formal Sign-Off Methodology and Abstraction Models to achieve 'end-to-end formal verification' and complete coverage during DVCon US, beginning later this month (Feb 26-Mar 1) at San Jose's DoubleTree Hotel. Oski will be present at Booth #205.

DVCon US technical program

Vigyan Singhal, Oski’s president and chief executive officer (CEO), will jointother verification experts on a panel titled, “Help! System Coverage is a Big Data Problem!,” to identify best practices for using verification methodologies (Wednesday February 28, 8:30am-9:30am, Oak/Fir).

Singhal will also join a colleague from Qualcomm and to present a technical paper, “Architectural Formal Verification of System-Level Deadlocks”, during the Formal Verification Use Models session (Wednesday, February 28, 10:00am-12:00pm, Fir).

A case study entitled, “Formal Verification of Silicon for Software Defined Networking,” will be offered by Oski user Saurabh Shrivastava, senior manager Hardware Engineering at Cavium during the Poster Session (Tuesday, February 27, 10:30am-12:00pm, Gateway Foyer).

Formal Leadership Summit at DVCon US

For the third consecutive year, Oski will host the Formal Leadership Summit  on Wednesday evening where leaders in Formal Verification will discuss the way formal affects verification.

This year’s summit will explore how formal verification is driving verification sign-off for designs across the industry. Experts will address trends where applications are finding success with formal verification, how adoption is growing and current challenges facing engineers. A post event summary will be available.

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