UltraSoC delivers trace for RISC-V

By Chris Edwards |  No Comments  |  Posted: January 28, 2018
Topics/Categories: Blog - Embedded, IP  |  Tags: , , ,  | Organizations:

UltraSoC has released its first implementation of processor trace for cores based on the RISC-V instruction set.

As well as a stand-alone IP module for integration with UltraSoC’s SoC architecture, the company offers a variety of packaged options to get RISC-V designers up-and-running quickly without necessarily using UltraSoC for other functionality. These range from a lightweight package that combines simple run-control with USB as the debug interface; to more sophisticated solutions with both run control and trace, and interfacing via either JTAG or UltraSoC’s proprietary non-intrusive, bare-metal USB. UltraSoC remains the only company that supports all of the main run control options offered within the RISC-V ecosystem.

Last June the company announced plans to develop processor trace, when it also detailed a trace specification to be considered for adoption as part of the RISC-V open standard. In September, UltraSoC announced that its embedded analytics IP will be available through the SiFive DesignShare ecosystem. In November, UltraSoC announced it has been selected for use in Microsemi’s RISC-V product range.

Rick O’Connor, executive director of the non-profit RISC-V Foundation, said: “RISC-V is redefining the SoC value proposition: a key part of that is building a much more open and robust ecosystem than developers have been used to. On the technical level, full availability of processor trace is a key part of that development ecosystem. Within the RISC-V Foundation, we’re working to standardize the interfaces to RISC-V cores that provide processor trace; we’re delighted to see UltraSoC supporting that effort, while also delivering commercially.”

Processor trace functionality allows the behavior of a program to be viewed in detail, instruction-by-instruction, and is a key requirement for system developers. The UltraSoC RISC-V trace encoder supports both 32 and 64-bit RISC-V designs.

Leave a Comment

PLATINUM SPONSORS

Synopsys Cadence Design Systems Mentor - A Siemens Business
View All Sponsors