Codasip updates processor-architecture tools

By Chris Edwards |  No Comments  |  Posted: January 23, 2018
Topics/Categories: Blog - EDA, Embedded, IP  |  Tags: , ,  | Organizations:

Codasip has launched the seventh generation of its Studio software for processor design and tuning, aiming to take advantage of the interest in RISC-V as a core instruction set for customized processors.

The company has used the Studio tools to create its own portfolio of RISC-V processors, employing it for design-space exploration and prototyping for specific applications, using custom extensions described in an architecture-description language.

Version 7 adds native support for Amba bus interfaces to ease the migration from existing processors such as those from ARM but employing existing peripheral IP cores. The company has also made improvements to clock-gating control for low-power design. The Codespace Eclipse-based IDE, and the underlying software tools, now include support for LLVM 5.0.

“Studio 7 is a big step forward for Codasip’s advanced processor creation technology, and will take the guesswork out of implementing the ever-expanding number of ISA options in the RISC-V specification. Studio can help generate processors well-suited to the widest range of application areas, from machine learning inference engines to host processor DSP offload, networking, and storage,” said Karel Masařík, CEO and co-founder of Codasip.

Leave a Comment

PLATINUM SPONSORS

Synopsys Cadence Design Systems Mentor - A Siemens Business
View All Sponsors