Microsemi sets up RISC-V partner program
Microsemi is putting more emphasis behind its backing of the RISC-V architecture with the creation of a partnership program intended to drive adoption of the architecture, which the company supports through soft cores for its FPGAs.
For the Mi-V ‘ecosystem’, Microsemi has recruited several software suppliers and has timed the formation of the group to coincide with the release of a collection of additional soft cores based on the RISC-V instruction set architecture (ISA).
“As a leader in RISC-V, we are pleased Microsemi is the first tier one vendor to build out a complete open RISC-V ecosystem, which not only supports our needs, but contributes to the entire development community,” said Jim Aralis, chief technology officer and vice president of advanced development at Microsemi. “Customers can now select RISC-V for their new designs knowing a tier one vendor committed to the success of this technology is providing all the necessary tools to confidently use RISC-V soft CPUs in their products.”
Among the members of Mi-V is RTOS provider Micrium. Jean Labrosse, co-founder and chief architect at Micrium, said: “As RISC-V continues to grow in popularity, we look forward to working closely with Microsemi to support accelerated adoption of its RISC-V soft CPU product offerings as well as the entire ecosystem’s RISC-V advancements.”
Alongside Micrium, Express Logic is supporting RISC-V through its ThreadX RTOS and Huawei is offering its LiteOS.
“The open source, royalty-free RISC-V instruction set creates a new business model for CPU designers that is garnering increasing interest and support,” said Linley Gwennap, principal analyst with The Linley Group. “By introducing the RV32IM CPU core with support from the Mi-V ecosystem, Microsemi will play an important role in boosting the adoption of RISC-V.”
Ted Speers, head of product architecture and planning for Microsemi’s programmable business unit, was appointed to the inaugural board of directors of the RISC-V Foundation in July 2016, and Ted Marena, director of SoC FPGA marketing, was recently sworn in as chair of the RISC-V marketing committee after serving as vice-chair since August 2016.
