Debug IP specialist UltraSoc has donated a specification for processor trace to try to provide the RISC-V ecosystem with a common way of ferrying runtime data to software tools.
“We’ve proposed to the RISC-V Foundation the creation of a format for instruction and for data trace,” said UltraSoc CEO Rupert Baines. “It’s one of the things missing from the current architecture. We’ve put it into the foundation for anyone to adopt and make an implementation. We have our own commercial implementation as a product but anyone can use the format and develop one in competition with us.”
Five processor-core vendors developing implementations that run the open-source RISC-V instruction set have said they will support the trace format. Andes, Codasip, Roa Logic, SiFive, and Syntacore are working with UltraSoc to put the specification together ready for submission to the RISC-V Foundation for potential inclusion as part of the reference processor implementation.
Karel Masarik, Codasip CEO, said: “As more of our customers adopt RISC-V, the need for a rich standardized ecosystem around deployment and debug is becoming a necessity. Getting these ecosystems in place is key to ensuring RISC-V becomes the first choice of development teams everywhere.”
Baines said there are plans to develop extensions for the optional parts of the RISC-V instructions, such as digital signal processor (DSP) operations. “There will be additional fields for things like the zero-overhead loops that are commonly found in DSPs as well as out-of-order instructions, which the current crop of cores don’t currently support.”