Smart code editor adds SystemVerilog support

By Chris Edwards |  No Comments  |  Posted: June 15, 2017
Topics/Categories: Blog - EDA  |  Tags: , , ,

Code-editor specialist Sigasi has added support for SystemVerilog to its Sigasi Studio tool, which uses a built-in parser to perform more reliable syntax highlighting and error checking.

Rather than use a regular expressions engine to highlight syntax as found in an editor such as Emacs, Sigasi Studio employs its own parser. This also makes it possible to perform tasks such as scope-aware signal and object renaming, detecting errors in function calls, and spotting syntax errors. For example, if a call is declared with two arguments but the developer only types in one, the software will flag the incomplete statement and it will also pick up on potentially misplaced semicolons.

Sigasi Studio's versions for languages such as Verilog and VHDL make function calls hyperlinks within the editor so that it is possible to click on them and go to the declaration. The SystemVerilog version includes support for the language's preprocessor macros, helping with development of UVM test-suites among other things.

Hendrik Eeckhaut, Sigasi's CTO, said: "SystemVerilog is a rich and complex design language, it is vital for designers to have a tool that understands the design context and gives errors and warnings as they type."

Adrie Diren of LMS Instruments, now Siemens, added: "The refactoring capabilities of Sigasi Studio are impressive. Finding and correcting errors and warnings, context sensitive search, code completion, encapsulating modules, adding signals to source files has really decreased development time."

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