DAC 2017 preview: Verific Design Automation

By TDF Editor |  No Comments  |  Posted: June 9, 2017
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EDA platform enabler Verific Design Automation will be highlighting its recent work with startup Baum at this year's Design Automation Conference to demonstrate how companies are leveraging its SystemVerilog, VHDL and UPF parsers.

Baum has used Verific solutions to build a new power analysis and modeling tool. Demonstrations will take place daily throughout the DAC 2017 exhibition (Monday June 19 – Wednesday June 21) from 1:00PM until 3:00PM at the Verific booth (#639) in the Austin Convention Center.

The booth will also host a demonstration of the latest version of Verific’s UPF Elaborator. This will show how users can take a UPF description to power pins and gates in the netlist.

Visitors can also learn about new capabilities in Verific’s UPF Parser/Analyzer that comply with the IEEE 1801-2015 standard (UPF 3.0) and versions 1.0, 2.0 and 2.1.

Verific is also a co-sponsor of ‘Verified’, a new DAC party with a verification theme being held on Tuesday June 20 from 8:00PM until 1:00AM a.m. at Easy Tiger. A limited number of tickets for both are available at the company's booth.

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