IEDM explores faces of 3D monolithic integration

By Chris Edwards |  No Comments  |  Posted: December 12, 2016
Topics/Categories: Blog Topics  |  Tags: , , ,  | Organizations:

What will 3D integration look like? Will it be the answer for high-end, high-density multicore processors or the low-cost option for smart sensor nodes? To some extent, the market has already spoken with the development of image sensor devices that attach processors to the light-sensitive chip using thru-silicon vias (TSVs).

A recent addition to the 3D image sensor came at the recent IEDM conference in San Francisco. A team from STMicroelectronics' imaging division described the first 3D-stacked device based on a backside-illuminated single-photon avalanche diode. The 128 x 120pixel prototype had a pitch of 7.83µm, making it the smallest so far for SPAD-type sensors. ST implemented the image-sensor layer on a 65nm, choosing 40nm for the processing electronics that sit on top. Aimed at biomedical applications such as endoscopy where small size and high sensitivity to photons are vital, the team kept the processing comparatively simple to focus on optimization of the pixel array. They were able to work with shutter times as short as 20ns.

A group from the National Nano Device Laboratories and the National Chiao Tung University in Taiwan explored deeper integration on the now mature 40nm node – but integrating novel technologies monolithically such as vertical resistive memory (RRAM) cells together with solar-energy harvesting. The researchers used a combination of annealing strategies tuned for low thermal budgets to create the multiple layers.

Polished surfaces

For the logic and I/O transistors, the team opted for a thin-body silicon-on-insulator structure, depositing a 20nm layer of silicon that is then given a flat surface using chemical mechanical polishing (CMP). They used far-infrared laser annealing on this and subsequent surfaces to keep annealing temperatures to no more than 400°C. The circuits on the base chip included a 6.8GHz voltage-controlled oscillator, implemented to try to demonstrate an RF capability for the monolithic integration technology, and power-management unit.

On top of the base layer, the researchers built the vertical RRAM matrix followed by a top layer used for sensors and a section of amorphous silicon germanium carbide for solar harvesting.

Working with the National Tsing Hua University, the National Nano Device Laboratories worked on a second monolithic 3DIC design based on two stacked layers of sub-10nm finFETs. For this design, the team used laser spike annealing, again working at no more than 400°C, arguing that device performance showed the process is viable. The transistors demonstrated a drive current of 386µA/µm for nMOS and 352µA/µm for pMOS devices, thanks partly to the use of a tall fin structure.

Both top and bottom layers had metal layers up to M3 on top of a high aspect ratio (AR > 7) single-grained silicon finFET. The surfaces for the transistors were plasma-structured and far-infrared laser annealed. Source and drain activation was also achieved using laser assistance. Transistors were defined using e-beam lithography.

Stacked cells

Working with the Georgia Institute of Technology, GlobalFoundries described work to overcome the performance deficit of upper-layer transistors compared to those grown on the base layer. The team opted for a layer split between nMOS and pMOS so that the routing in the lower half of sandwiched could be reserved for local, intra-cell interconnect.

The stacked cell reduced the number of tracks for a cell from nine to five. The fifth track was used for interlayer vias and to connect signals to the cells with one track in each layer devoted to power/ground and the remainder for intra-cell routing. The work found space saving of around 45 per cent assuming the interlayer vias were no more than 50nm wide. Increasing metal width led to a quadratic increase in area consumption and a rapid loss of benefit from 3D integration. If the space savings could be realized, the researchers claimed the area savings would pay off in terms of reduced inter-cell routing overhead.

Leave a Comment


Synopsys Cadence Design Systems Mentor - A Siemens Business
View All Sponsors