DVCon Europe to examine role of UVM, SystemC in system-level verification

By Chris Edwards |  No Comments  |  Posted: September 13, 2016
Topics/Categories: Blog - EDA, Embedded  |  Tags: , , , ,  | Organizations:

DVCon Europe opens its doors for the third time in the third week of October (19-20). Taking place in Munich once more the conference and show is a local event that its organising committee sees as having global influence: thanks to the emphasis on mixed-signal, functional-safety and system-level design on the continent.

The combination of application expertise and verification experience among the speakers and delegates means that it is set to be a key event for plotting the course of UVM, SystemC and verification in general. Alongside dedicated in-depth sessions on SystemC and UVM, the technical program contains papers on subjects down to gate-level simulation.

Oliver Bell, conference chair and Intel's head of system-level and functional verification, says: "The conference goes from virtual prototyping down to the gate level."

Matthias Bauer, program chair and senior manager for system-level, functional verification and design for test at Infineon Technologies, says the conference received more than 60 papers to consider this year. Just over 30 of those are to be presented as full technical papers. Instead of poster sessions, DVCon Europe this year is trying the idea of lightning talks. "These will take five to seven minutes and the speakers will be able to talk to users during the break," he adds.

"We changed the setup of the technical programme a little this year," Bauer adds. "We introduced some subcommittees: system level; design verification and validation; mixed signal; and functional safety."

Prototyping focus

Bell says a major focus of the conference this year is virtual prototyping because of the growth in importance of embedded software. "The use of virtual prototyping is maturing. It's no longer a question of the right thing but getting to the next level, getting the most efficient usage out of the technique."

Bauer says virtual prototyping is now being used industrially in many different forms: "The use-cases include design specification; system validation; firmware development; and performance analysis."

Going hand in hand with virtual prototyping is the evolution of SystemC, Bell explains: "Virtual prototyping based on TLM 2.0 is a good example of how the community is working around DVCon. Last year, we found an overwhelming interest in this, which led to the creation of the SystemC Evolution day in Munich in May. For this DVCon we will have a follow up on that: a special SystemC track focusing on virtual prototyping challenges."

Design teams are also using SystemC to streamline the flow from architectural definition to implementation. "We are seeing IP-Xact being used for generation purposes. One paper is on power extensions where SystemC is used to generate UPF."

Streamlined flows

Martin Barnasconi, last year's chair and cluster leader for system-level mixed-signal methods at NXP, says: "People are sticking these different phases together and using standards like IP-Xact to help. There is now much more focus on efficient and automated flows.

"At DVCon Europe we are exploring how to bring the different pieces of verification together. We also see a need for standards, such as extensions to TLM. One set of extensions is aimed at more efficient simulation based on parallel processing."

The ability to bring engineers from different teams together at the conference and its various networking opportunities helps to drive the standards process, Barnasconi adds: "We bring up proposals for improvements in SystemC and extensions."

Bell adds: "People talk about the deficiencies of SystemC. DVCon Europe is a catalyst for possible solutions. If there is common agreement this is catalyst for driving improvements in the standards. It adds to the whole ecosystem. EDA vendors can adopt the standards, customers come together and have a good result."

UVM's growing role

UVM and its role in moving into full-chip and system-level verification will come under the spotlight at the Munich conference and show. Bauer says: "For UVM there are a lot of topics that start at the system level, where people use UVM methodology for virtual prototyping. Other papers talk about making it more usable: for example, using generation methods on the RTL to get more convenient UVM. There are also papers on using UVM for analog and mixed-signal design. There is a big variety of UVM topics."

Barnasconi adds: "What may be different compared to other DVCons [around the world] is the strong industrial interest not just in mixed-signal but system-level design. Europe is trying to see what universal means in UVM. You can have UVM as a methodology layer but, in terms of implementation, use extensions tuned to a particular application area. UVM now is not only SystemVerilog but analogue extensions, software and ESL extensions."

The keynote session, as well as the technical program, reflects the increasing interest in functional-safety topics, Barnasconi says: "Hobson Bullman of ARM will examine challenges on the methodology side in general. The second keynote, given by Juergen Weyer of NXP will look at applications such as self-driving cars. Both reflect the growing importance of software. It's not a separate department anymore."

Bell concludes: "From a visitor point of view you can go deep on a topic. You can get all the different aspects of a subject or use DVCon to get an overview. And you can use opportunities such as the gala dinner for networking."

Leave a Comment

PLATINUM SPONSORS

Synopsys Cadence Design Systems Mentor - A Siemens Business
View All Sponsors