DTCO points to sub-10nm optimizations
Papers at the recent VLSI Symposia in Honolulu looked at the tradeoffs between design and manufacturing as process geometry scales below 10nm – to the extent of moving to more complex processing if it means improving overall areal density.
In its work on design-technology co-optimization (DTCO), GlobalFoundries scaled standard-cell designs down to the N5 or 5nm node – effectively at the 24nm fin-pitch limit.
At N10, the designers assumed a metal-one pitch of 48nm, which is within the scope of double patterning, albeit with restricted routing. But the team decided that a more flexible routing, despite calling for a third exposure to offer tight tip-to-side spacing, would yield a small overall cell. Instead of having to use a four fin-per-transistor 9-track cell to accommodate wiring, this could be scaled down to 7.5 tracks and so offer better areal scaling. In principle, it yields just over a halving in layout area for the 10nm candidate process compared to 14nm.
Such a strategy proved impractical for simulations of the N7 node – calling instead for horizontal M0 and vertical M1 wiring. The split in levels with both metal layers providing pin access within the cell shifted the design of an example AOI112 cell towards a square six-track cell.
Power routing will present more problems in the N7 generation because of unidirectional wiring – as traditional approaches do not fit well. This may involve further changes to standard-cell layout as well as how EDA tools deal with place and route.
One-way routing with EUV
Expected to be the first node for which the much-delayed EUV technology could be ready, N5 will still require unidirectional routing according to GlobalFoundries’ work. This node will need more research as scaling down the cell area may call for the ability to form contacts to gates over active fins. An alternative is to push the scaling of the lowest layer of metal to further squeeze the height of the standard cell library – down to perhaps 5 tracks.
Although the GlobalFoundries team has looked into N3, this one is fraught with problems because it will mostly require nanowires. These could lead to a major shift in layout approach if the vertical structure turns out to be practical.
The node is also expected to have a wiring pitch of 24nm because this is the effective scaling limit of copper wiring. Beyond that parasitic resistance and capacitance are expected to become too high to make copper wiring useful.
Power beats area
In its work on DTCO for the N7 node, Qualcomm also looked at reducing cell height by moving to designs that allowed for fewer fins. However, the company’s DTCO work focused on balancing not just area and manufacturing but power consumption and thermal envelope.
The Qualcomm team argued thermally limited sustained performance is now a vital metric. In effect, the dark-silicon problem posed by ARM CTO Mike Muller more than five years ago is really beginning to bite. As a result, the Qualcomm researchers developed thermal models for their proposed process choices to try to come up with the best mixture of features for N7.
The results pointed towards a choice of threshold voltage that implies lower peak clock speed than is possible on the target process to avoid excessive thermal throttling and leakage, which for single-core operation hurt execution throughput for the full task. However, the threshold voltage cannot be taken too high as it becomes too hard to complete jobs in time even with multicore operation.
Through modifications of the process to cater for metal-interconnects parasitics as well as an emphasis on fin-depopulation, Qualcomm argued that it is possible to remain on the same area reduction line as that seen in the shift from 14nm to 10nm.
