Intento uses graphs to optimize analog blocks

By Chris Edwards |  No Comments  |  Posted: June 6, 2016
Topics/Categories: Blog - EDA  |  Tags: , , ,  | Organizations:

Startup Intento Design has launched an analog-circuit migration and optimization tool based on a technique that is meant to reduce significantly the amount of simulation needed to develop viable implementations.

Ramy Iskander, CEO and founder, said the tool uses graph-theory techniques developed at the LIP6 research center in Paris, France to automatically size the devices within a circuit topology for the target process, with optimization focused on finding the DC operating point.

Iskander said: “The DC operating point is underestimated in the literature. But when we get the DC operating point, we get performance.”

The approach used by the ID-Xplore tools uses, on average around 200 calls to a Spice simulator. Traditional sizing and optimization techniques demand on the order of 1500, he claimed. “We don’t give the whole netlist to the simulator. We construct the design transistor by transistor.

“We have mimicked the thought process of the designer. The graph is a mapping from the design parameters to sizing and biasing,” Iskander added.

To use the tool, the designer defines the schematic in Cadence Virtuoso or Mentor Graphics’ environment. The tool then uses the schematic to start sizing the transistors. According to Iskander, the designer can select desired parameters such as power consumption, performance and area. The tool will then generate a number of candidate circuits.

To promote evaluation by startups, Eric Laurent, business development director, said they can run for two months with support for €25,000 in order to get designs running. The amount can be used against the full cost of the tool if the company adopts it long-term.

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