ARM aims at low-end compute with 32bit Cortex-A

By Chris Edwards |  No Comments  |  Posted: February 23, 2016
Topics/Categories: Blog - Embedded, IP  |  Tags: , ,  | Organizations:

ARM has gone back to the 32bit realm for its latest Cortex-A processor core, aiming the device at a new generation of low-cost platforms inspired by the success of the Raspberry Pi as well as wearables.

The Cortex-A32 provides a way of building a comparatively low-cost microcontroller based on the ARM architecture able to run virtual-memory operating systems such as Linux. The Cortex-M and Cortex-R are designed for operating systems that address physical memory directly, albeit with some level of protection between tasks.

Ian Smythe, director of marketing programs in ARM's CPU group, said: "There is now a wide range of platforms offering affordable compute, not just the Raspberry Pi. Their support for rich operating systems has opened up embedded development to a much wider range of developers than ever before. We have now made Cortex-A more affordable and accessible to many more designs."

Although it is a version 8 Cortex-A (v8A), the A32 supports a 32bit memory model. "We expect many of these embedded devices to remain 32bit for the foreseeable future," Smythe claimed.

Although v8A implementations have been 64bit, Smythe said: "We added over a hundred new instructions on the 32bit side. Compared to v7, there are new floating-point instructions, new crypto instructions for SHA and AES algorithms and enhanced media video through new Neon instructions."

According to Smythe, the A32 provides about 25 per cent more performance per milliwatt compared to the A7, with the greater gains coming from the floating-point additions although there is a small uplift in integer performance as well. In principle, the core can be assembled in a quad-core configuration run at up to 1GHz on an advanced process.

A more likely target will be lower clock speeds, Smythe said: "Running at 100MHz, it will take up less than a quarter of square millimeter on 28nm."

Smythe said the Trustzone implementation is derived from the hypervisor-oriented model of the Cortex-A processors rather than using the recently launched Trustzone-M architecture. It does not support Big-Little.

Leave a Comment

PLATINUM SPONSORS

Synopsys Cadence Design Systems Mentor - A Siemens Business
View All Sponsors