Cadence shifts emulation to the data center

For its latest iteration of the Palladium emulation system, Cadence Design Systems has designed the hardware to fit into the corporate data-center, making changes to virtualization and availability aspects of the system’s design to suit that environment.

Michał Siwiński, vice president of product management in Cadence’s system and verification group, claimed: “This is the first ever data center centric emulation platform: something that is available globally is one of the key tenets.”

Cadence claims the new hardware offers a five-fold throughput advantage over predecessors and capacity up to nine billion gates, expecting the emulator hardware to be split between multiple simultaneous jobs. The Palladium Z1 platform can execute up to 2304 parallel jobs.

“For our advanced SoC designs we are facing thousands of verification payloads of varying sizes from dozens of different projects,” said Daniel Diao, deputy general manager of the Turing processor business unit at Huawei.

Designed for the rack

The design is based on a standard data-centre rack-of-blades architecture with hot-swappable logic cards to allow the system to keep running if one of the them fails. Although the job using the failed blade will probably need to be restarted after a failure, others should continue unaffected, providing better overall uptime than existing emulation platforms, according to Siwiński.

A number of the subsystems, such as power delivery, have been designed to be redundant to further boost MTBF. “We’ve redesigned elements that had the biggest impact on failure,” he said.

Compared to the Palladium XP II, the new machine exhibits less than one-third the power consumption per emulation cycle, Cadence claimed. The external hardware interfaces have now been fully virtualized using a ‘virtual target relocation capability’. This enables remote access of fully accurate real-world devices as well as virtualized peripherals such as Virtual JTAG.

Siwiński said the platform offers up to 22 different use models, in-circuit emulation, simulation acceleration, with support for hot-swapping between simulation and emulation, dynamic power analysis, and OS bring-up for ARM-based SoCs running at 50x the performance of conventional emulation.