Expanding role of UVM takes center stage at DVCon Europe

By Chris Edwards |  No Comments  |  Posted: October 8, 2015
Topics/Categories: Blog - EDA, IP  |  Tags: , , , , ,  | Organizations:

In a little over a month’s time, DVCon Europe takes place in Munich, Germany. According to leading members of the program committee it will provide a venue for engineers to debate and learn about the verification challenges and approaches that suit the continent’s skills in system design.

Cluster lead at NXP Semiconductors and DVCon Europe general chair Martin Barnasconi says: “The reason we do DVCon Europe is because of the difference in the local market to other regions. We have our own competence areas and application domains. We are quite strong in the system-level space and in mixed signal. And we are reflecting that back on issues in verification.

“We are using current practices as starting points, but seeing how we can make verification more encompassing, rather than being IP or semiconductor centric. We want to move up to the system level,” Barnasconi added. “If I take a relevant application domain for us, such as automotive, the semiconductor content is continually increasing. The challenge is what some call systems of systems. How to bring the semiconductor devices in the ECUs together. The verification challenge is not just addressing each of those ICs but the whole system.

“Today, UVM is well suited to IP verification. But we have to explore how we can bring that to the next level.”

Software’s increasing role

Principal verification engineer at Infineon Technologies and DVCon Europe program chair Matthias Bauer adds: “It’s not just the hardware content. The software component is getting bigger. And we have to look at verification for safety. That’s something we will address within the conference. The approach is not dramatically new methodologies but to adapt methods we have had for a while.”

Barnasconi says UVM provides a useful framework that can be extended beyond its home of SystemVerilog-based IP verification – an area that the conference will tackle.

“We need to think beyond SystemVerilog,” says Barnasconi. “That’s where the challenge is if you ask me. System-level people might use SystemC, C++ or Matlab Simulink. The methodology concept behind UVM is something we should build upon to make it more applicable to other disciplines.

“In the conference there is a tutorial on UVM in SystemC. Teams are trying to bring the methodology to different languages. It underlines the ‘U’ in universal in my view. We also have the trend towards software-driven verification. We need to enable this software layer can be used within sequences defined in UVM.”

Completing the V

Another aspect of verification to be covered in the conference is the extension of advanced verification methodologies to analog and mixed-signal design, through techniques such as real-number modeling, Bauer says.

“Also, the focus is not just verification but validation as well, with a number of papers at the conference. Can I use some of the verification methodologies from the pre-silicon phase to post-silicon. Show how test cases from verification can be used for bringing up silicon in the lab and to harmonise your environments. That can be brought together with requirements-driven verification so that you can see at any time that the traceability for safety verification still met.”

Bauer says the shift towards safety-focused verification is driving requirements-based verification using top-down specifications in a V-model model.

For those not working directly on safety-related systems, Barnasconi sees a trend that builds on coverage-based design: “We are seeing papers that embrace a coverage-driven approach and showing how to you define your coverage. I think over the years we will see the trend move to metric-driven and further to requirements driven.”

As well as the extensions into system-level and mixed-signal design, Bauer says papers will look at increasing efficiency with UVM. “How can I make the environment more powerful? Or reduce the number of patterns to make it faster? There is also one paper that looks at maybe using a ’UVM-lite’ to get engineers much faster into the methodology.”

Multi-language issues

Barnasconi says by bringing many engineers together, the conference along with its attached exhibition provides a valuable opportunity to discuss other pressing issues. “Today, we have to deal with a multi-language environment, both for the design and for the testbench. For the design, people know how to mix languages. But, in the testbench, it is a bit more problematic. With UVM, if you want to plug in a Matlab model, it is not easy to see how that works.

“As an industry, we need to do a better job of addressing the multi-language problem, to seamlessly integrate languages in a testbench environment,” Barnasconi adds.

“What we also have with the conference is the exhibition. It’s a very rich exhibition - a lot of companies signed up to show their tools. It provides a venue where a lot of vendorscan meet engineers. We can offer a good mix of technical papers, tutorials and in two days visits all the vendors that are active in the verification, system design and consultancy space.”

Bauer concludes: “DVCon Europe is a platform where people can talk and discuss the issues that we have in the industry.”

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