DVCon Europe initial technical program unveiled

By Chris Edwards |  No Comments  |  Posted: September 25, 2015
Topics/Categories: Blog - EDA, IP  |  Tags: , , ,  | Organizations:

DVCon Europe has published the technical program for its upcoming November conference in Munich, Germany.

Sponsored by Accellera Systems Initiative, the two-day conference running from 11 to 12 November 2015 is intended to bring the latest verification methodologies, applications and techniques to an audience of chip architects, design & verification engineers, and IP integrators.

The first day (Wednesday, 11 November 2015) provides 15 tutorials on a variety of SoC verification methodologies and techniques. The tutorials include sessions on advanced UVM usage, system-level modeling with SystemC, how to bring UVM into SystemC, as well as techniques on high-throughput debug and how to verify the correctness of assertions in SystemVerilog.

The technical sessions on the second day will cover 36 papers and posters split across several tracks, covering a variety of issues and techniques, ranging from checks on SoC memory maps and mixed-signal verification through to strategies for projects that need to comply with the ISO 26262 or DO 254 standards.

As well as a full technical conference, DVCon Europe will host an exhibition with demos from training partners, and design tool and IP service providers. A gala dinner will be held on the evening of the first day of the conference.

Early bird registration discount is available through October 1st, 2015. Registration is sponsored by Mentor Graphics and is available online at: www.dvcon-europe.org/registration. The conference will be held at the Holiday Inn Munich City Center, Hochstrasse 3, 81669 Munich, Germany.

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