Agnisys is adding automated verification of SoC registers to its IDesignSpec tool for defining and specifying register maps and behaviours, deploying both a dynamic and a formal version.
Using an embedded formal engine supplied by OneSpin, ARV-Formal takes the register specification information and the RTL code for the registers and their control logic and performs a formal proof to ensure they match.
Taking advantage of the exhaustive nature of modern formal verification technology, ARV-Formal automatically generates assertions directly from the specification and executes them using the integrated formal engine, eliminating the need to access an external formal product.
ARV-Sim is the corresponding tool for verification based on dynamic simulation and integrates with Incisive from Cadence Design Systems, Mentor Graphics’ Questa, and VCS from Synopsys. ARV-Sim is designed to remove the often tedious and error prone manual creation processes needed for building UVM testbench and stimulus sequences. ARV-Sim provides the positive and negative sequences automatically for each register’s specified behavior, testing interface between the registers and the application logic as well as the the register implementation itself.
ARV-Sim supports testing of special registers, such as those used for interrupts, and aliased registers where logic is used to replicate data to other registers in the memory map. The tool generates sequences for these special registers, taking the specifications either from the IDesignSpec tool itself or from a variety of input files, ranging from SystemRDL and IP-XACT standard register types through to custom specifications supplied in Word or Excel files, using either standard or custom mappings to manipulate the specification information into a form suitable for the tool.
“IP-XACT is very tedious to create by hand,” said Anupam Bakshi, founder and CEO of Agnisys. “Many of our customers use our tool IDesignSpec for register data. It’s simple to use and can help capture special properties that are needed to describe special register behavior.
“Agnisys and others are leading an effort under Accellera to add missing constructs in SystemRDL to support many things that are required by modern day register design and verification,” Bakshi added. Shadow registers are among the types of register not currently supported by SystemRDL, he added, necessitating the creation of additional properties by designers.
ARV-Sim in use
Allegro Microsystems has used ARV-Sim to verify the many different types of register that the company uses in its mixed-signal products, such as Hall-effect sensors and power ICs, bringing the simulation and test data into its overall coverage and metrics-driven verification (MDV) flow.
“All our new designs use IDesignSpec for specification generation, automatic HDL generation and UVM register model generation for the register/memory blocks,” said Allegro design verification manager Khalid Chishti. “This methodology enhancement has already brought much-needed consistency from common template-based Word-document specifications, [as well as] productivity and efficiency gains during the product development cycle across all projects. Our designs also have additional challenges that are not uncommon in the industry. For example, features like memory shadowing, aliasing, timers, customer locking and security.
“These added features required us to spend time in the verification of these blocks since the UVM built-in library tests do not address these additional design features of the register blocks. The ARV-Sim product provides a complete standalone verification solution for register/memory blocks that is completely turnkey,” he added.