CEA-Leti has launched a design center called Silicon Impulse with the intention of lowering the entry barrier to using the FD-SOI process.
Olivier Thomas, CEA-Leti design center project leader, said: “The aim of Silicon Impulse is to create a link between fundamental research and product prototyping and production. Our goal is to create an ecosystem where we can provide all services needed to start from an idea and get to a product.”
Silicon Impulse aims to build an network of IP and services around the process and will offer IC design, emulation and test services along as well as access to multi-project wafer (MPW) shuttles, kicking off with ST’s version of the FD-SOI process.
As well as working on FD-SOI, the design center aims to provide access to other technologies supported by CEA, such as resistive RAM, MEMS, silicon photonics, and 3D integration, with a focus on low-power design.
Design to MPW
Leti CEO Marie-Noëlle Semeria, claimed: “With Silicon Impulse’s one-stop-shop platform, 28nm FD-SOI heterogeneous, low-power design becomes a reality for the IoT community.”
Ali Erdengiz, senior business development manager for Silicon Impulse, said the center would offer a range of engagement types up to full-service design. “But if someone has access to PDKs and knows what to do and just need access to MPW, we can provide that.”
Thomas said the team can bring expertise in designing circuits that take advantage of the forward and reverse body biasing techniques that help FD-SOI deliver lower-power devices. “We have some algorithms are not today implemented in EDA tools,” said Thomas. “We have a lot of research on this. For example, with the circuit we developed for ISSCC 2014. For this circuit, there were a lot of techniques developed to use back bias automatically.”