Synopsys claims it has overall leadership in the race to enable finFET-based designs.
According to Swami Venkat, senior director of marketing for the Galaxy design platform at Synopsys, the tool suite has been used for 90% of finFET designs that are going into volume production. This metric sets aside designs that have been done to prove other design flows, as test chips or to validate IP blocks.
The company says that all the foundries offering finFET processes have used and qualified the Galaxy Design Platform, including GlobalFoundries, Intel Custom Foundry, Samsung and others. It says that more than 20 companies have between them completed over 100 finFET tape-outs using the platform.
Among them are implementations of ARM’s recently announced Cortex-A72, -A57 and -A53 cores by HiSilicon Technologies, targeting TSMC’s 16nm process. One of these tapeouts had more than 50 million instances, including four ARM Cortex-A72 quad-core processor clusters, each of 1.6 million instances.
Among the techniques used to achieve the design were physical guidance from Design Compiler Graphical to give tight correlation with IC Compiler, layer-aware optimisation in Design Compiler and IC Compiler, and concurrent clock and data optimization in IC Compiler.
HiSilicon also took advantage of IC Compiler’s variation-aware multisource clock tree synthesis technology, and advanced net and device delay models, including resistive shielding on long nets and waveform propagation analysis, to model signal distortion and hence give tighter silicon correlation.
Other aspects of the tool suite used included finFET grid-placement and route rule support; advanced parasitic extraction for signoff accuracy with StarRC; and PrimeTime’s ADV physically-aware ECO guidance with IC Compiler.
“We have selected the Galaxy Design Platform for all of our finFET implementation because of the superior quality of results delivered by the platform,” said Yu Lin, senior director of technology platform engineering at HiSilicon Technologies said in a statement.