A startup with what it claims to be a novel and more cost-effective approach to making finFETs that should easily scale to the ultimate limit of this type of device is looking for funding and partners to take its currently theoretical design into not just 14nm/16nm processes but provide 28nm with a mid-life kicker.
“We have device designs and process integration recipes,” claimed FinScale CEO Jeff Wolf, but the company has not reached the point of making test chips.
Although “there isn’t a reliable enough modeling simulation in TCAD for a full 3D device”, Wolf claimed the theory and manufacturing expertise behind the architecture are sound. “We have designs that have been put together based on in-depth experience at many prior process nodes. Our CTO Victor Koldyaev was [a fellow] at PDF Solutions where he was their process troubleshooter, helping their clients optimize for performance.”
Koldyaev moved from PDF Solutions in 2008 to Innovative Silicon, which developed single-transistor memories based on finFETs.
Funding for test chips
FinScale’s aim is to develop the test chips needed to demonstrate the manufacturability and performance of the device with customers and partners.
“The story behind this is that we set out in the beginning to design the last finFET of the silicon era,” said Wolf, which led to the idea of what the company calls the quantum finFET (qfinFET).
The qfinFET does not work differently to a conventional finFET, the name comes from the techniques used to model what the ‘ultimate’ silicon device should look like. Koldyaev used quantum-mechanical techniques to calculate the minimum size of an undoped silicon device that would operate successfully.
“The performance should be very good but we have yet to experiment,” said Koldyaev. “People ask how I can be sure that the interface will be good. We have some proprietary knowledge that is not widely known in the industry on quantum effects.”
FinFET model changes
In the course of doing simulations an error emerged in the TCAD software Koldyaev used to calculate quantum-level effects. The error was corrected and helped provide the answer of 3.5nm for the silicon fin thickness, which he said conflicts with conventional wisdom on the ultimate dimensions of the finFET.
“The classical model is wrong. This quantum model says you can’t put holes into a smaller space than 3.5nm,” Koldyaev claimed.
This, in turn indicated a minimum channel length of 10nm, although the use of new materials could provide further scaling. Based on silicon, a 10nm device with 3.5nm-thick fins would have an off-state current of approximately 100nA/µm, said Koldyaev, suitable for a high-performance device. Extending the channel length, short of altering materials for different work functions, would provide lower-leakage transistors. “We don’t want to change the silicon film. It’s simple and we like simple.”
Wolf said: “We built a structure around that and we found we could move it backwards. We have detailed designs at 22nm, 14/16nm and we are now working on 28/32nm, to help those processes live forever. We open up a lot of degrees of freedom. The existing finFET designs have been around for a while and the processing for them has many drawbacks that need to be solved.”
Wolf said the company has one patent so far on the manufacturing technology.
The manufacturing techniques chosen by FinScale tries to overcome the problems, such as leakage, caused by the sloped sides seen on devices made by Intel among others as well as reducing the number of litho steps. One issue with current processes is that “the fins end up standing alone after the etching process”, said Wolf. “It’s very hard to clean the fins. In our process, the fin never stands alone.
“The 2D self-aligned process allows you to build the fin with only one litho step [on 14/16nm a process] rather than double patterning,” Wolf continued. “We are using standard fab modules and standard materials. They are existing, known techniques. People will look at this and go ‘wow’ and wonder why they didn’t think of it.”
As well as being rectangular the fin is deposited in a process that does not demand that the completed fin is fully exposed. The isolated fins in conventional process suffer a high risk of tipping over and sticking to each other. As a result of the different approach, “we are able to make the fins thinner than existing processes”, said Wolf.
Koldyaev said one key element of the process is the way that it etches out of shallow trench isolation (STI) oxide rather than depositing the STI after fin construction, which is the conventional technique. He said the FinScale approach would provide straighter sides, high aspect ratios, and low surface roughness. “STI etch is a basic, fundamental industry process,” he stressed.
In effect, the fin is defined as the result of etching out strips of isolation oxide deposited between the source and drain. Once space for them has been etched out, the fins can be formed from the exposed silicon substrate before finally being covered by the gate stack.
STI etch has been proposed by other manufacturers for defining the central section of a fin that is then epitaxially extended. The FinScale approach, however, forms the fin within the original silicon substrate.