Synopsys uses virtual prototyping kits to kick start IP integration

By Chris Edwards |  No Comments  |  Posted: June 2, 2014
Topics/Categories: Blog - EDA, Embedded, IP  |  Tags: , , , ,  | Organizations:

Synopsys is porting its IP to a series of virtual prototyping kits in a plan to cut the amount of time that it takes to integrate new high-speed interfaces such as USB 3.0 and PCI Express. The kits combine the company’s own ARC 32bit processors or ARM’s Cortex-A57 for 64bit applications with models of the interface IP blocks themselves running on the HAPS virtual prototyping boards.

Although the kits are designed to provide subsystems that are ready to run code for early driver and firmware development, the aim of the kits is not to enforce a particular clock and reset strategy on an SoC so that everything is built around the IP.

“We are under no illusion. Every single customer and SoC will have their own strategy to deal with the clock, reset and test logic. Every IP core just has to fit in,” said Johannes Stahl, director of marking for virtual prototyping at Synopsys. “But to integrate an IP they first have to understand it.”

Stahl said by starting with the kits a lot of work that will be needed during the project can start much earlier than usual. Using the kits, hardware engineers can understand what makes the IP tick and firmware engineers can tune the drivers and build code on top that will be needed for integration as well as exercising the SoC during verification.

“We provide a reference design where we provide RTL code they can read, showing this is one way of doing it that is working,” said Stahl. “The team can figure out what are the changes they need to make. It’s much better than having to read the manual to get started. “At the subsystem level we define the control schemes to power up and down correctly so that the interface is working.”

IP integration

“The idea of ‘out of the box’ is almost a contradiction when integrating with an existing design,” said Stahl. “But we have done the initial work for them. When customers start with a new design they will often reuse their old processor subsystem and interface IP. But when they change their interface IP from say USB 2.0 to USB 3.0 they have to start anew with that IP.

“The semiconductor guys are being asked to understand the applications space, and spend more time and effort on the software. They have less and less time to look at all the different interfaces. This gets them up and running,” said Stahl. “Normally they have to spend a lot of time reading specifications and the manual to get their own prototype up and running, before they can really do anything with the IP.

“We want to provide these kits at a very aggressive price point and reduce their internal effort so it just becomes a no-brainer as part of their overall IP transaction.”

The first IP-Accelerated kits will appear in July and August aimed at the most commonly encountered I/O standards in SoC projects such as USB 3.0, with other cores added during the rest of the year. “Our goal was not to release one or two and see how it goes. We have a roadmap of making these things available,” Stahl said.

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