Uptake of formal techniques in verification to be outlined in keynote

By Luke Collins |  No Comments  |  Posted: October 17, 2013
Topics/Categories: Conferences  |  Tags:  | Organizations:

After decades of research, formal techniques are now having a real impact on the verification of billion transistor SoCs, Pranav Ashar, CTO of Real Intent, will tell an upcoming conference.

“The comprehensive and precise verification of things like clock domain interfaces, of constraints, of reset and initialization, of power management, of RTL implementation idioms, of coding practices etc depends fundamentally on symbiotic algorithms that have been developed in this community,” said Ashar in a video previewing his keynote address to next week’s FMCAD – the Formal Methods in Computer-Aided Design conference. 

Ashar feels that although the design community appreciates the value of these formal-methods based approaches to static verification, the research community is less aware of the positive impact of its work on design.

“The bigger message in that keynote is about the aspects of the problem and the solution that are working well, and areas [to which] more research needs to be directed, where static methods are still in their infancy in terms of deployment.”

Here’s the video:

Ashar’s keynote, Static Verification Based Signoff – A Key Enabler for Managing Verification Complexity in the Modern SoC, will be given on Wednesday 23 October at the FM-CAD conference, which is being held at 
the University Place Hotel & Conference Center, in Portland, Oregon.

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