Cadence parallelizes FastSpice for large-scale mixed-signal checks

By Chris Edwards |  2 Comments  |  Posted: October 9, 2013
Topics/Categories: Blog - EDA  |  Tags: , , ,  | Organizations:

Cadence Design Systems has developed an extension to its range of Spectre FastSpice tools that splits the processing of simulation across multiple computers to speed up the job of verifying mixed-signal designs across multiple process corners without manually cutting the design into segments.

Christian Malter, director of technology solutions and business development for Cadence EMEA, said Spectre XPS had, for a large SRAM design, “solved the design 30 times faster than the next-fastest competitor”.

Cadence’s development of Spectre XPS was driven by the explosion of corner cases caused by the inclusion of multiple power states simulated against different temperature and process conditions as creating a bottleneck in mixed-signal simulation and verification.

“You have to run in different process corners, which multiplies the number of simulations that you have to do,” said Malter.

“Our engineers found a way to partition and parallelize the simulations. It splits the device into segments and runs those segments on different machines in parallel for all the different corner cases,” Malter explained.

The simulator works with existing Spectre-compatible process design kits (PDKs) and models and is able to handle the impact of IR drop on device performance by unifying the simulation of the power grid and the circuit elements.

Spectre XPS will be sold as separate tool alongside other versions of the FastSpice simulator.

2 Responses to Cadence parallelizes FastSpice for large-scale mixed-signal checks

  1. Hillol Sarkar on October 16, 2013

    This is a great news for us. We can reduce optimization time.
    At present it takes 12 hours to optimize 200 transistors over PVT. (4 Threads)

    Hillol.Sarkar@ago-inc.com
    http://www.ago-inc.com

  2. Pingback: Multicore fastSpice extends reach | Tech Design Forum

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