CDNLive Boston to tackle mixed-signal design, host exhibit

By Chris Edwards |  No Comments  |  Posted: August 12, 2013
Topics/Categories: Blog - EDA, PCB  |  Tags: , , , , ,  | Organizations: , ,

The CDNLive series of Cadence Design Systems user conferences moves to the east coast of the US for the end of August before heading across the Pacific to China and India in the early autumn. Taking place at the Radisson Hotel & Suites in Chelmsford, MA on 27 August, the conference will feature user-authored papers, Cadence tutorials, a designer expo and kicks off with a pair of keynotes.

The first keynote will be given by Cadence senior vice president of R&D in the custom IC and simulation organization Tom Beckley, who will deal with the problem of mixed-signal design complexity. Beckley has spoken at previous CDNlive events not just about the implementation side of the custom-IC flow but on techniques to save on verification such as wreal modelling using the real-number calculation facilities in high-speed logic simulators for SystemVerilog and other languages.

In the second keynote, David Harame, chief technical executive for development and enablement at IBM will talk about the company’s specialty 200mm foundry technologies, which now reach down to the 90nm node, including a silicon germanium BiCMOS process that has been picked by Tektronix for a generation of 70GHz oscilloscopes to be delivered in 2014.

At an event in Bangalore last year, Harame described how IBM used the specialty technologies available in its 200mm fab at Essex Junction, VT to build low-power, high-speed RF switches for the front-end of a 4G handset. The designers combined silicon-on-insulator (SOI) technology for signal processing circuits with bulk RF silicon for the RF transistors. Other applications for the high-speed RF bulk and SiGe processes include millimeter-wave gigabit communications links in the 10 to 100GHz range that are now being proposed for mobile backhaul.

In the technical sessions that follow, Cadence and user engineers will cover a range of topics, from the use of modgens in Virtuoso to implementing high-speed memory interfaces on PCBs. The full agenda is online together with a registration page.

 

* CDNLive Boston will also feature a Designer Expo, where users will be able to get up close and personal with tools from a host of vendors.

Real Intent will be in hand to exhibit its two product families – Ascent products for functional verification before synthesis, and Meridian products for performing advanced sign-off verification on issues that cannot be tackled by simulation or static timing analysis.

The Ascent family includes Ascent Lint, a high-capacity linting tool that performs syntax and semantic checks on complex RTL; Ascent Implied Intent Verification, which uses automatic check formulation followed by deep-sequential formal analysis to do early functional verification; and Ascent X-Verification System, which detects and isolates X-propagation issues early in Verilog RTL.

The Meridian family includes Meridian CDC, which performs comprehensive structural and functional analysis to ensure that signals crossing between asynchronous clock domains of a design are received reliably; and Meridian Constraints, which helps manage constraints using constraint validation, template generation, coverage analysis, equivalence checking and timing exception verification.

Real Intent staff will be on hand throughout CDNLive Boston to discuss the various offerings.

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