Three Accellera proposals aim for better TLM

By Chris Edwards |  No Comments  |  Posted: July 30, 2013
Topics/Categories: Blog - EDA, Embedded  |  Tags: , , , ,  | Organizations: , , ,

STMicroelectronics, ARM and Cadence Design Systems have made three contributions to the SystemC language working group of the Accellera Systems Initiative, providing potentially a new standard interface for modeling interrupts, an applications programming interface (API) for examining registers; and a novel approach to memory-map modeling.

The contributions comprise fully working application programming interfaces (API) and implementations, as well as documentation and examples, released under an Apache 2.0 open-source license and available online at http://forums.accellera.org/files/.

“These new interfaces are crucial to strengthening the ESL ecosystem. As a step towards interoperability driven by ST, ARM and Cadence, these proposed standards dramatically reduce risks and efforts associated with the integration of virtual prototypes. Eliminating the need for adapters will increase virtual prototype simulation performances, enable sooner and faster hardware-software integration, and therefore improve product time-to-market,” said Philippe Magarshack, executive vice president of design enablement and services at STMicroelectronics.

John Goodenough, vice president of design technology and automation at ARM, said: “By addressing a key gap in the model-to-model interface and by enhancing tool integration, these proposed contributions further help in ensuring virtual prototypes can be predictably and consistently integrated.”

The first proposal addresses the need for better interoperability among SystemC TLM 2.0 models and proposes a standard interface to model interrupts and wires at the transaction level.

The second proposal defines a standard interface between models and tools to support register introspection, enabling any tools that understand it to display and update register values. This interface works in a mix of different user-defined register classes to support platforms integrating heterogeneous models from various model providers. Accellera sees this capability is a key enabler for integration and debug of embedded software on pre-silicon virtual prototypes.

The third proposal introduces an approach to reconstruct system memory maps as seen from initiators, enabling ESL tools to support hardware-software debug on complex virtual platforms, for which understanding of the memory maps is instrumental. It addresses the challenge that system memory maps depend on the interconnection of models, which can lead to each system initiator having its own view of the map.

Within the Accellera Systems Initiative, ARM, Cadence, and ST said they plan to work with other companies to refine and fully standardize these proposals.

Add Comment Register



Leave a Comment

PLATINUM SPONSORS

Mentor Graphics GLOBALFOUNDRIES Synopsys Samsung Semiconductor Cadence Design Systems
View All Sponsors