Altera outlines process roadmap for ‘Gen 10′ FPGAs

By Chris Edwards |  No Comments  |  Posted: June 10, 2013
Topics/Categories: Blog - EDA, PCB  |  Tags: , , , , ,  | Organizations: , ,

Altera has disclosed a number of the features that will make it into the top end of its upcoming ‘Generation 10′ family of field-programmable gate arrays (FPGAs), which will be made on either the 14nm finFET process provided by Intel or TSMC’s 20nm planar CMOS process.

Later this year, Altera expects to have a test chip that will act as the precursor to prototypes of the Stratix 10 series. All of the upcoming families will have ‘SoC’ versions that include embedded-processor cores. Altera is aiming for 1GHz operating frequency for the Stratix FPGAs with more than four million logic elements and 56Gbit/s serial transceivers. The company plans to provide versions that use 3D-IC techniques to add large amounts of DRAM as well as ASICs.

The first products to appear will be the Arria 10, aimed at communications systems, which will use the TSMC process, offer up to 1.15 million logic elements and incorporate a dual-core ARM Cortex-A9 processor subsystem. The transceivers on these products will operate at up to 28Gbit/s.

I/O inversion

Ty Garibay, vice president of engineering for silicon system development, said of the Arria 10: “Structurally, the product is quite novel at a physical level. It is the first one that has been built where the I/O and serdes [serial/deserializer interfaces] were column based and internal to the physical die.

“Gen 10 is intended to be flip-chip packaged [rather than wire-bonded]. We take advantage of that in floorplanning to bring them into the centre and distribute the I/Os much more easily, which has helped improve utilisation. Typically on an FPGA you have I/O taken to the outside, with the core logic sitting in in the middle. With this new architecture we distribute it a little more efficiently through the fabric,” Garibay explained.

Altera expects to have customer samples of the Arria 10 in 2014 but the parts are supported in the company’s Quartus II development environment. Software support for Stratix 10 will arrive in 2014.

Stratix 10 plans

Garibay said: “For Stratix 10, this is more a technology announcement. We are going to feature a new high performance fabric architecture. The performance is beyond what you can get with straight process scaling. We are building a new fabric architecture that allows natively, within the same process, higher frequency operation. But we are combining that with the dramatic performance improvement of moving to finFET.

“When we saw the opportunity that we were going to have with the Intel process we decided to combine these two technologies together and get a big bump. It goes to the message that we are optimizing each product line very much for the process. In the next 12 months, we will do designs in 28, 20, 14 and 55nm,” said Garibay, with the 55nm process aimed at lower-density, low-power programmable-logic devices.

“For Stratix 10, the low leakage of finFET is very attractive,” Garibay said, adding that active power is getting attention. “I believe it’s the first time that we are doing some sort of active power management. The range of operating voltages that are possible with 14nm should allow for a reasonably effective dynamic voltage and frequency-scaling function.

“Transistor-level design with finFETs is very interesting,” Garibay added. “In four or five months’ time we will know a lot more and we will have a test chip later this year. There aren’t many companies who are going to be able to do full-custom design at 14nm and working with Intel will give us a significant advantage.”

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