Fabless, IP designers need process simulation tools, says Coventor CTO

By Luke Collins |  1 Comment  |  Posted: May 28, 2013
Topics/Categories: Design to Silicon, Blog - IP  |  Tags: , , ,  | Organizations:

Early adopters of advanced process technologies need to be able to model process variability for themselves, so they can understand how it is likely to impact their designs, according to David Fried, CTO of process simulation company Coventor.

“Too many early users of these processes have been burned by thinking that if a design is DRC-clean they will get what they want,”  he said. With fabless companies, especially in the mobile sector, under pressure to start designing with new processes before they have been finalised, insights into the impact of process variability could enable defensive design techniques that would mitigate the effects of process variability issues.

Fried sees a number of uses for process modelling in this context. For example, a team working on a fast SERDES in an evolving process might need to know how the different ways in which the process could evolve would affect their design’s performance and noise margins. Physical IP vendors might want to understand how the evolution of process parameter distributions over time would impact their offerings. And manufacturing specialists could use the approach to analyse the way in which one layer influences the printability of another.

For teams working in design enablement, this kind of process modelling would enable them to work out how a process change would challenge an established set of design rules, or to add a design rule now in case a potential change becomes a reality.

“People will be able to decide whether they should put a design rule out there now in case they make a particular change later,” he said.

Fried argued that the approach could lead to “better PDKs sooner”, and pointed out that although only a handful of companies worldwide are likely to have the depth of relationships with foundry partners that would give them access to such sensitive foundry data now, “every fabless company gets a compact model, and that is incredibly sensitive data.

“PDKs are evolving – ten years ago you couldn’t get reliability data.”

The company has updated its SEMulator 3D tool by adding a different way of modelling devices. To date, the tool has modelled using voxels, unit blocks that are built up using a behavioural description of the process to define the 3D shape of the device. This approach is fast, but lacks the fidelity needed to model some advanced devices. Coventor’s response has been to add a ’surface evolution’ modeling technique, a more accurate structural representation based on describing a surface using differential equations.

“The fact that we have unified those two approaches in one platform is part of the achievement,” said Fried.

Coventor has used the technique to model two fab processes that are being applied in more complex ways in advanced devices. The first is a multiple etch stage, through many materials. According to Fried, the tool has always been able to handle etch processes, and its voxel-based approach will remain relevant for “99% of cases”, but for some very complex devices it will be useful to switch from the voxel-based etch approach to a surface-evolution based multi-etch approach.

The second fab process that is benefiting from the new approach is selective epitaxy, where the additional accuracy means that it is now possible to model crystal growth at different rates in different lattice directions.

“These sorts of capabilities are foundational to figuring out how we will build these complex devices,” said Fried, adding that he is working with customers to define which fab processes it should model next using this new technique.

The SEMulator 3D tool includes ‘virtual metrology’, to extract the dimensions of devices produced by its virtual processes, and a field solver to extract capacitance matrices. Improved automation means that users can ‘produce’ devices at multiple corner  cases, and then extract the electrical characteristics to build up a picture of performance variability.

One Response to Fabless, IP designers need process simulation tools, says Coventor CTO

  1. Pingback: Fabless, IP designers need process simulation tools, says Coventor CTOCoventor | Coventor

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