Lithography combined with not double, but triple and quadruple patterning could soon be a fact of life, according to a research note from Gartner Semiconductor & Electronics.
Analyst Dean Freeman says that with each shrink, multi-patterning (Guide) is going to cost the industry a lot. About $500m per future node for each logic fab with 45,000 wafer starts per month. To put that into context, TSMC’s Fab 15 has a target capacity of more than 100,000 wsps.
“The delay of extreme ultraviolet lithography (EUV) will drive significantly higher lithography costs. Alternative technologies have the potential to minimize the higher costs, but they are still several years away,” he writes.
The note goes on to say that EUV “is the closest to implementation, most likely at the 10nm node”. Two other candidates remove the need for double patterning: e-beam lithography and directed self-assembly (DSA) lithography. But they are further behind in terms of maturity and investment.
All three, says Gartner, could reduce lithography costs by 30-40%. But there is another devil in the detail.
A diagram in the note shows that Gartner generally remains skeptical about all alternatives, except moves to drive 193nm immersion lithography (193i) to smaller nodes. Intel has already said that it is confident of taking a mixture of multi-patterning and 193i to 10nm.
It is, admittedly, a crude reading but the ‘Likelihood of Success’ column suggests EUV is still a 50:50 play while its rivals are at around one-in-four.
EUV lithography is getting funding. For example, research groups such as imec continue to announce advances toward production-readiness and GlobalFoundries is building a research facility in New York State with EUV as a key focus for it.
But even the technology’s adherents acknowledge an ongoing challenge with source powers. These are edging toward and around 20W, but to use chemically amplified resists that enable the densest patterns, many experts believe the industry will need source powers of 500 to 1000W by 2016. It is a tough ask.
This latest forecast reiterates the need for further research into mitigating the amount and cost of multi-patterning required beyond 20nm, probably until 7nm.
And, regardless of broad commitment to EUV, it continues to position that as semiconductor’s leading mañana technology.