CDNLive EMEA opens next week on Monday 6 May, providing delegates with an opportunity to find out what their peers are doing with Cadence Design Systems’ tools in actual projects.
Beginning after lunch on Monday, the program starts with a series of technical overviews by Cadence engineers of a number of tools and flows in the company’s portfolio and will include workshops on transaction level modeling, advanced analog and RF IC design, and algorithmic modelling for PCB design.
On Tuesday morning, Cadence president and CEO Lip-Bu Tan kicks the keynote sesson. He is followed by Keith Clarke, vice president for embedded processors at ARM, and X-FAB CEO Rudi de Winter, who will focus on analog design.
In the following technical sessions, STMicroelectronics will be among those following the mixed-signal theme with a look at the company’s Virtuoso-based smart-power design flow. Engineers from NXP Semiconductor will focus on clock optimization in 65nm. Located close to a number of German automotive companies in Munich, the event is a suitable venue for a look at the ISO26262 safety standard by Freescale Semiconductors.
Looking forward to the finFET processes, a session by ARM will look at 14nm finFET design and tools. The event finishes at lunchtime on Wednesday with best-paper presentations.