DATE: Early shift to finFET processes challenges IP development strategies

By Luke Collins |  No Comments  |  Posted: March 20, 2013
Topics/Categories: Conferences, Blog - EDA, IP  |  Tags: , , , , , ,  | Organizations:

An early shift to finFET-based processes (Guide) is making the process of developing supporting IP libraries more challenging, according to Joachim Kunkel, senior vice president and general manager of the solutions group at Synopsys.

Joachim Kunkel

Joachim Kunkel

Kunkel argues that the 20nm planar processes that were supposed to provide the next improvement step after 28nm have not delivered the performance and power consumption improvements that users had hoped for, prompting them to consider moving directly to 16nm or 14nm finFET based processes instead.

“FinFET delivers all the things that 20nm promised but didn’t,” said Kunkel. “When we went from 28nm to 20nm all we got was integration density, not the increased performance or decreased power we had expected. For some customers, that increased density makes sense. But with finFET you are getting power savings, performance and integration improvements, and that is why there is a tremendous pent-up demand to move to finFET.”

Manufacturers have responded with rapid moves to finFET processes. Intel detailed an SoC variant of its finFET process at December’s IEDM, while TSMC said in October 2012 that it would accept risk production lots for its 16nm finFET process in November 2013. Samsung is gathering support from tool vendors for its finFET process, and GlobalFoundries has been benchmarking the performance of its 14XM finFET process.

Synopsys is now working with Samsung and GlobalFoundries to try out its IP libraries on test chip runs on early versions of their finFET processes, to provide early and intermediate validation points. It has already run test chips on TSMC’s 20SoC planar process, which delivered early insights into building robust IP on a process with some of the same manufacturing challenges as the finFET processes, such as the requirement to use double-patterning lithography (Guide) and complex planarisation strategies.

The new finFET processes represent both a geometry shrink and a change in transistor architecture, and so Kunkel says that it is up to the EDA vendors to make life as simple as possible for their users.

“The thing that is difficult is doing two changes at once, so we have to make sure that on the tools side design is as easy as possible and on the IP side, users don’t have to deal with the manufacturing complexity of the processes. The foundries hide the complexity behind the physical design kits (PDKs), and we hide everything else.”

Synopsys has had to adjust its IP development strategy, running test chips using early, version 0.1 PDKs, and offering them to customers for use in their early test chips, even if the IP is not based on the finalised PDK.

“The effort of developing something on shaky ground is always more than on solid ground – but that is the price you have to pay,” he said. “We know that we will have to do a second test chip once the PDK reaches 1.0.”

But Kunkel was keen to stress that finFET IP is still a work in progress.

“Don’t mix up doing some test chips with the availability of production-ready IP,” he said. “Our intention is always to have something production-ready shortly after a foundry announces the availability of the 1.0 PDK.”

Has the introduction of a completely new transistor architecture made IP development more difficult? Some circuit architectures have had to be rethought to accommodate the different characteristics of the vertical, rather than planar, device, but the bigger issue has been accommodating the manufacturing challenges of the very dense processes, such as double patterning, variability and mitigating the effects of manufacturing variations.

“Density fill is a task that takes much longer than it used to,” Kunkel said.

For the users of the IP that Synopsys develops, design with finFET processes may not carry too much additional complexity.

“Have we stumbled on anything which makes it look like design on finFETs will be very very difficult? Absolutely not.”

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