DATE: Dark clouds gather over 3D integration, panelist tells conference

By Luke Collins |  No Comments  |  Posted: March 19, 2013
Topics/Categories: Conferences, Blog - EDA  |  Tags: , , , , , ,

The chip industry could face problems as the foundry business and the packaging industry struggle for control of 3D integration technologies, Naveed Sherwani, president of Open-Silicon, told the DATE conference this morning.

“Our nice collaborative industry has reached the point where I see dark clouds on the horizon,” he said. “On the [silicon] interposer, there’s going to be a war because real [revenue and volume] numbers are at stake. Are the interposers made by the foundries or by the packaging companies? Suppose the interposer war is won by the foundries, it will marginalise the packaging companies.”

Sherwani argues that 2.5D integration, using silicon interposers, is going to be important because it will enable companies that want to produce medium volumes of custom chips to start using advanced processes again – in other words, to make the ASIC approach accessible after a period in which it has become prohibitively expensive for all but the largest-volume customers.

He says that the number of companies that have been prepared to take on large SoC projects has declined over recent years because of the rising cost of design. In response, he proposes that SoC designs are de-integrated into discrete blocks – standard CPUs, application-specific processors, I/Os etc, each on a separate die – which are then assembled on an interposer alongside the 20%  of the design which is unique to the customer.

“IP costs have gone from $2m to $8m, and the second cost is NRE, which has risen from $600k at 45nm to $4m at 14nm,” he said. “That’s $12m just to start an ASIC. This is the reason why customers are interested in 2.5D.

“Customers used to design 30% of their chips, and now it is more like 15%. The rest of the stuff is IP that we can procure for them.”

Taking this approach would also reduce schedules, because it would be unnecessary to re-prove the established blocks alongside the customers’ novel work.

“Taping out everything pushes the schedule from three months to nine to 12 months,” Sherwani said. “We found we were wasting huge amounts of the back-end team’s time taping out the same design again and again.”

The fact that the individual chips may cost an extra $2 to $4 each because they’re built using interposers, rather than monolithic integration, matters less than the total cost of ownership for the design, at least for medium volumes.

Sherwani argues that the prospect of 2.5DIC integration at a lower total cost of ownership than monolithic integration may also tempt venture capitalists back into funding silicon start-ups.

“I am hoping that 2.5DIC integration will allow the VCs back in,” he said. “They used to invest $20m for a $200m return but that has become $60m for an $80m return. With 2.5DIC there is hope that we can bring the costs down. If we can agree on some standards – for example for I/O systems – then people may be able to innovate on the part that matters to them.”

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