The latest update to Mentor’s HyperLynx PCB design and analysis suite opens up the intriguing prospect of a market developing in design rule decks for checking advanced board layouts.
The DRC system in HyperLynx is set up to automate checks for EMI, signal and power integrity issues on high-speed designs, embedding the intelligence in the tool so that it can be used earlier in the design process and by people with a wider variety of skill levels.
According to David Wiens, business development manager in Mentor’s systems design division, “DRC as a checking engine is a faster way to find the bigger problems.”
Relatively simple issues, such as breaks in signal return paths or potential crosstalk between nets can be highlighted interactively, while more complex issues emerge when the tool is run in batch mode. “In our roadmap, the idea is to have this running in parallel with the design process.”
One version of the latest HyperLynx release includes the canned rule sets provided by Mentor, while a second version enables users to write their own rule decks.
“Because the tool allows you to write your own version of the rules, people can codify their own best-practise intellectual property in the tool.”
Wiens gave two examples of how this might work: a large semiconductor company is using the tool to embed its expertise in designing boards for its processors in a rule deck that it can give to third parties to help them ensure that their own boards will work with its chips; an aerospace company wants to ensure as much redundancy in its designs as possible, so is writing rules to ensure that redundant circuit traces are laid out as far apart as possible.
“And we’re investigating the idea of a market for these rules,” he said. Dave Kohlmeier, senior product line director for analysis products in the same division as Wien, added: “Industrial consultants might be interested in developing sets of rules for niche applications.”
Mentor has rolled even more IP up into the latest HyperLynx release with a DDRx design wizard for use before layout begins. The wizard ‘interviews’ the user about the way they want to implement DDR and then sets up the simulation models to do the necessary signal integrity and timing analysis. This latest version supports DDR3L and DDR3U supply voltages by incorporating the required de-rating tables, timing models, and voltage levels.
“The DDR wizard helps users to do a quick set-up,” said Kohlmeier. “We talk about ‘fastest route to quick results’.”
Figure 1 Measured (at left) vs simulated eye diagram for a multiboard system (Source: Mentor Graphics)
Other enhancements to the tool include faster simulation, and enough accuracy to handle a 12.5Gbit/s backplane design from Molex that includes causal material models, copper surface-texture contributions, via models, mode conversion and reflections from integrated S-parameter models of connectors. Mentor says its approach to simulating PCBs is better than some others because it does not oversimplify the structure of short transmission lines, which are often used as ‘meanders’ to equalise the length of signal-pair traces.