Calypto Design Systems has combined the Catapult high-level synthesis (HLS) tool that it acquired from Mentor Graphics last year with elements of its PowerPro software to focus on the demand for lower-power SoC designs.
Shawn McCloud, vice president of marketing at Calypto, claimed: "There is tremendous synergy between the individual products. The results is the first HLS product that focuses on power as well as performance."
In the latest release of PowerPro, version 6.0, Calypto improved the speed of its analysis by conducting more work at RTL. "It's ten times faster than going to the gate level," said McCloud.
This technology has now gone under the hood of Catapult LP where it is used to work out the potential for adding power-saving functions such as clock gating to the logic that Catapult synthesises.
"Today, many optimisations are made at the gate level and lower. But the real impact on power occurs when you move up to the architectural level. You can look at the options for resource sharing and the tradeoffs between parallelism and operating at lower frequencie," said McCloud. "We have now got a flow where we can explore hardware architectures with the mindset of power."
As the Catapult user tries out different architectural approaches, the RTL analysis that PowerPro applies to the logic generated by the HLS tool, will show how much potential there is for clock gating in each as well as the options for putting memories into a power-saving drowsy mode – a feature recently added to the PowerPro tool.
"Memories can esily consume 50 per cent of the power in many DSP applications," said McCloud.
The accuracy of the tool can be altered so that, as the user narrows the architecture search to a few options, the accuracy of the switching estimation performed by the power analyser can scale up. McCloud said the accuracy of the power analysis is generally within 15 per cent of a full gate-level simulation.