DATE notebook: Constraints smooth path for FPGA synthesis

By Chris Edwards |  1 Comment  |  Posted: March 15, 2012
Topics/Categories: Conferences, Design to Silicon, Blog - EDA, - Product  |  Tags: , , , ,

Blue Pearl Software has extended its reach into the world of field-programmable gate array (FPGA) design and verification with a project that has culminated in a tighter integration between its timing analysis tools and the Synopsys Synplify Pro tool.

The integration is designed to focus the logic optimizations performed by Synplify Pro to make it easier to fit large designs into a target part and ensure that it is not over-constrained.

Shakeel Jeeawoody, director of product marketing at Blue Pearl, explained at DATE: "What we do is look at each path in a design and determine whether the path is activatable within a single clock cycle. If not, that is deemed a 'false path'. The second thing we do is identify which are multicycle paths. Then having identified those accurately, what we do is generate constraints using the SDC format that identify that these are paths that Synplify does not have to optimise. This ensures you meet timing more quickly because the tool is not attempting to optimize logic paths unncessarily."

Jeeawoody added: "We work at the RTL level. And we understand the functionality of the design. If you go from state machines down to netlist level you lose that visibility. That is why we can find these complex multicycle paths."

Focusing synthesis is becoming increasingly important as designs reach into the multimillion-gate region thanks to the imminent arrival of 28nm-process paths – and compile times potentially stretch out from hours into days.

However, the links between RTL analysis and synthesis are not quite as straightforward in the FPGA domain as in the ASIC-design world. The project needed close cooperation between Blue Pearl and Synopsys.

Jeeawoody said: "We work with Altera and Xilinx but with Synopsys we have brought collaboration to the next level."

Ellis Smith, CEO of Blue Pearl, said: "It's a big issue that we are helping with. Synthesis tools for FPGA weren't built from the beginning to accept timing constraints. They used to look at timing purely at the gate level."

The problem with passing constraints to FPGA synthesis is that the RTL-gates conversion first goes through a mapping phase which is followed by logic optimization, at which point the tool will read in SDC data that takes into account this mapping.

Jeeawoody explained: "We intercept the first phase of synthesis. We gather the register map and then generate the SDC. Typically, you don't intercept this intermediate data but you have to use to generate SDC for the second phase.

"This approach is also possible with Xilinx and Altera: We are working with them," Jeeawoody added.

Last month, Blue Pearl released the 6.0 edition of its main software suite with extra support for SystemVerilog and VHDL, as well as FPGAs. The company will be running its next workshop on the update at its Santa Clara HQ on April 19. Software evaluations are also available now.

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